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HSP9520, HSP9521
Data Sheet May 1999 File Number
2811.5
Multilevel Pipeline Registers
These devices are multilevel pipeline registers implemented using a low power CMOS process. They are pin for pin compatible replacements for industry standard multilevel pipeline registers such as the L29C520 and L29C521. The HSP9520 and HSP5921 are direct replacements for the AM29520 and AM29521 and WS59520 and WS59521. They consist of four 8-bit registers which are dual ported. They can be configured as a single four level pipeline or a dual two level pipeline. A single 8-bit input is provided, and the pipelining configuration is determined by the instruction code input to the I0 and I1 inputs (see instruction control). The contents of any of the four registers is selectable at the multiplexed outputs through the use of the S0 and S1 multiplexer control inputs (see register select. The output is 8 bits wide and is three-stated through the use of the OE input. The HSP9520 and HSP9521 differ only in the way data is loaded into and between the registers in dual two-level operation. In the HSP9520 when data is loaded into the first level the existing data in the first level is moved to the second level. In the HSP9521 loading the first level simply causes the current data to be overwritten. Transfer of data to the second level is achieved using the single four level mode (I1, I0 = `0'). This instruction also causes the first level to be loaded. The HOLD instruction (I1, I0 = `1') provides a means of holding the contents of all registers.
Features
* Four 8-Bit Registers * Hold, Transfer and Load Instructions * Single 4-Stage or Dual-2 Stage Pipelining * All Register Contents Available at Output * Fully TTL Compatible * Three-State Outputs * High Speed, Low Power CMOS
Applications
* Array Processor * Digital Signal Processor * A/D Buffer * Telecommunication * Byte Wide Shift Register * Mainframe Computers
Pinout
HSP9520, HSP9521 (SOIC, PDIP) TOP VIEW
I0 1 I1 2 24 VCC 23 S0 22 S1 21 Y0 20 Y1 19 Y2 18 Y3 17 Y4 16 Y5 15 Y6 14 Y7 13 OE
Ordering Information
PART NUMBER HSP9520CP HSP9520CS HSP9521CP HSP9521CS TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 24 Ld PDIP 24 Ld SOIC 24 Ld PDIP 24 Ld SOIC PKG. NO. E24.3 M24.3 E24.3 M24.3
D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 CLK 11 GND 12
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HSP9520, HSP9521 Block Diagram
I0
D0 - D7
8
REG. A1
REG. A2
CLK MUX MUX REG. B1
8
Y0 - Y7
I1
REG. B2
OE
S0 S1
Pin Descriptions
NAME VCC GND CLK DIP PIN 24 12 11 I TYPE DESCRIPTION The +5V Power Supply Pin. A 0.1F capacitor between the VCC and GND pin is recommended. The device ground. Input Clock. Data is latched on the low to high transition of this clock signal. Input setup and hold times with respect to the clock must be met for proper operation. Data Input Port. These inputs are used to supply the 8 bits of data which will be latched into the selected register on the next rising clock edge. Data Output Port. This 8-bit port provides the output data from the four internal registers. They are provided in a multiplexed fashion, and are controlled via the multiplexer control inputs (S0 and S1). Instruction Control Inputs. These inputs are used to provide the instruction code which determines the internal register pipeline configuration. Refer to the Instruction Control Table for the specific codes and their associated configurations. Multiplexer Control Inputs. These inputs select which of the four internal registers contents will be available at the output port. Refer to the Register Select Table for the codes to select each register. Output Enable. This input controls the state of the output port (Y0 - Y7). A LOW on this control line enables the port for output. When OE is HIGH, the output drivers are in the high impedance state. Internal latching or transfer of data is not affected by this pin.
D0-7
3-10
I
Y0-7
21-14
O
I0, I1
1, 2
I
S0, S1
23, 22
I
OE
13
I
2
HSP9520, HSP9521
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input or Output Voltage Applied . . . . . . . . . . GND -0.5 to VCC +0.5V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 67 SOIC Package . . . . . . . . . . . . . . . . . . . 77.0 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to 5.25V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Standby Power Supply Current Operating Power Supply Current Input Capacitance Output Capacitance
VCC = 5.0V 5%, TA = 0oC to 70oC SYMBOL VIH VIL VOH VOL II IO ICCSB ICCOP CIN CO VCC = 5.25V VCC = 4.75V IOH = -6.5mA, VCC - 4.75V IOH = +20.0mA, VCC = 4.75V VIN = VCC or GND, VCC = 5.25V VOUT = VCC or GND, VCC = 5.25V VIN = VCC or GND, VCC = 5.25V Outputs Open f = 5.0MHz, VIN = VCC or GND, VCC = 5.25V, Outputs Open (Note 2) FREQ = 1MHZ, VCC = Open, All Measurements are Referenced to Device Ground TEST CONDITIONS MIN 2.0 2.4 -10 -10 MAX 0.8 0.5 -10 -10 500 12 12 12 UNITS V V V V A A A mA pF pF
AC Electrical Specifications
PARAMETER Clock to Data Out Mux Select to Data Out Input Setup Time (DO-7/10-7) Input Hold Time (DO-7/10-7) Output Enable Time Output Disable Time Clock Pulse Width NOTES:
VCC = 5.0V 5%, TA = 0oC to 70oC (Note 3) SYMBOL tPD tSELD tS tH tENA tDIS tPW (Note 4) TEST CONDITIONS MIN 10 3 10 MAX 21 20 20 13 UNITS ns ns ns ns ns ns ns
2. Power supply current is proportional to frequency. Typical rating for ICCOP is 2.4mA/MHz. 3. AC Testing is performed as follows: Input levels: 0V and 3.0V, timing reference levels = 1.5V, input rise and fall times driven at 1ns/V, output load CL = 40pF. 4. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major design and/or process changes.
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HSP9520, HSP9521 Timing Waveform
t PW CLOCK (CLK) tS INST (I0 - I1) tS DATA (S0 - D7) tH tH t PW
MUX SEL (S0 - S1) t PD OUT (Y0 - Y7) t SELD THREE STATE CONTROL THREE STATE OUTPUT (Y0 - Y7) OE t DIS t ENA (HIGH IMPEDANCE) 1.7V 1.3V 1.5V
TABLE 1. INSTRUCTION CONTROL I1 I0 HSP9520 HSP9521 S1 0
A1 B1 A1 B1
TABLE 2. REGISTER SELECT S0 0 1 0 1 HSP9520 OR HSP9521 B2 B1 A2 A1
0 1
0
0
A2 B2 A2 B2
1
0
1
A1
B1
A1
B1
A2
B2
A2
B2
A1
B1
A1
B1
1
0
A2 B2 A2 B2
1
1
All Registers Hold
All Registers Hold
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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